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[VHDL-FPGA-Verilog] UART_communication

Description: it s a document where described rs232 communinication between pc and fpga . it describe the vhdl structure of uart driver in fpga that allow communication between this devices
Platform: | Size: 206848 | Author: seif | Hits:

[Embeded-SCM Develop] Virtex-5EMAC

Description: This application note describes a system using the Virtex™ -5 Embedded Tri-Mode Ethernet MAC (Ethernet MAC) Wrapper core on a Xilinx Virtex-5 ML505 development board. The system provides an example of how to integrate the Virtex-5 Embedded Tri-Mode Ethernet MAC and the Virtex-5 Embedded Tri-Mode Ethernet MAC wrapper using a hardware design to target the development board, and a PC-based Graphical User Interface (GUI) to control the demonstration platform.-This application note describes a system using the Virtex ™ -5 Embedded Tri-Mode Ethernet MAC (Ethernet MAC) Wrapper core on a Xilinx Virtex-5 ML505 development board. The system provides an example of how to integrate the Virtex-5 Embedded Tri- Mode Ethernet MAC and the Virtex-5 Embedded Tri-Mode Ethernet MAC wrapper using a hardware design to target the development board, and a PC-based Graphical User Interface (GUI) to control the demonstration platform.
Platform: | Size: 492544 | Author: zhang | Hits:

[VHDL-FPGA-Verilog] FPGA-based-function-generator

Description: 本论文设计的任意波形发生器所要实现的基本功能： (1)输出波形的种类：正弦波、方波、三角波、锯齿波、脉冲波、手绘任意波形、任意公式波形。 (2)输出波形每一通道的频率、幅值、偏置都可以由用户调节，并且可以设置多个通道信号之间的相位差。 (3)编辑波形的方式有：设置参数、输入公式、手工绘制通信波特率的全部功能在PC机上实现。 -In this thesis, the arbitrary waveform generator to achieve the basic functions: (1) the type of output waveform: sine, square, triangle wave, sawtooth, pulse, arbitrary waveform hand, any formula waveform. (2) The output waveform of each channel' s frequency, amplitude, offset can be adjusted by the user, and you can set the phase difference between multiple-channel signal. (3) the way the waveform editor: set parameters, enter the formula, hand-painted communication baud rate of the PC, all functions in the implementation.
Platform: | Size: 589824 | Author: loutao | Hits:

[VHDL-FPGA-Verilog] Serial-communication-with-PC

Description: 基于FPGA的用VHDL语言编写的串口与电脑通信程序-FPGA-based serial port using VHDL language and computer communication program
Platform: | Size: 494592 | Author: 飞虎队 | Hits:

[VHDL-FPGA-Verilog] linux-power-pc

Description: running linux on power pc processor in virtex4 fpga in ml403 boards
Platform: | Size: 284672 | Author: ali | Hits:

[VHDL-FPGA-Verilog] FPGA-Communication-Framework-.tar

Description: 这是来自开源网站OpenCores的程序，版权归作者所有，仅供学习交流。一个上位机软件源程序，和一个FPGA硬件核的源程序（<600slices），上位机软件可以通过UDP/IP连通FPGA实现通信。-This is from the open source the website OpenCores the program belongs to the author, only learning exchanges. A host computer software source code, and an FPGA hardware core source (< 600slices), PC software via UDP/IP connectivity FPGA to achieve communication.
Platform: | Size: 24762368 | Author: 郑通 | Hits:

[USB develop] USB-FPGA-communications

Description: CY7C68013-A实现PC机与FPGA的USB通信例程-CY7C68013-A USB communication routines between PC and FPGA
Platform: | Size: 7155712 | Author: 赵秦川 | Hits:

[Other Embeded program] down

Description: FPGA的音频上位机下载程序，已经验证过了-FPGA-PC audio download programs, has already been verified
Platform: | Size: 1523712 | Author: 车龙 | Hits:

[LabView] PC-to-LCD-DE2

Description: the code describe how to conect from PC to LCD in FPGA by code C#
Platform: | Size: 1024 | Author: DDD | Hits:

[VHDL-FPGA-Verilog] FPGA

Description: 参加竞赛的FPGA双目测距的源码，包含上位机源码-Contest the FPGA binocular ranging source, including PC Source
Platform: | Size: 6045696 | Author: sunyongchang | Hits:

[VHDL-FPGA-Verilog] fpga-usb-verilog-test

Description: 红色飓风开发板中USB测试源码部分，包含说明文档，FPGA的verilog代码，cy68013固件程序，上位机测试程序。实现USB回环测试，可作为usb开发的参考文件-Red hurricane development board of the USB test source code, including documentation, FPGA verilog code, cy68013 firmware program, PC test program. Realization of USB loopback test, which can be taken as reference to the development of USB file
Platform: | Size: 15900672 | Author: 贾程序 | Hits:

[Software Engineering] FPGA-Prototyping-By-Verilog-Examples

Description: HDL (hardware description language) and FPGA (field-programmable gate array) devices allow designers to quickly develop and simulate a sophisticated digital circuit, realize it on a prototyping device, and verify operation of the physical implementation. As these technologies mature, they have become mainstream practice. We can now use a PC and an inexpensive FPGA prototyping board to construct a complex and sophisticated digital system. This book uses a learning by doing approach and illustrates the FPGA and HDL development and design process by a series of examples. A wide range of examples is included, a simple gate-level circuit to an embedded system with an 8-bit soft-core microcontroller and customized 110 peripherals. All examples can be synthesized and physically tested on a prototyping board. -HDL (hardware description language) and FPGA (field-programmable gate array) devices allow designers to quickly develop and simulate a sophisticated digital circuit, realize it on a prototyping device, and verify operation of the physical implementation. As these technologies mature, they have become mainstream practice. We can now use a PC and an inexpensive FPGA prototyping board to construct a complex and sophisticated digital system. This book uses a learning by doing approach and illustrates the FPGA and HDL development and design process by a series of examples. A wide range of examples is included, a simple gate-level circuit to an embedded system with an 8-bit soft-core microcontroller and customized 110 peripherals. All examples can be synthesized and physically tested on a prototyping board.
Platform: | Size: 17083392 | Author: Alexander | Hits:

[Home Personal application] utosnet_latest.tar

Description: The uTosNet framework aims at providing a very fast method for interfacing physical components, such as motor drivers, ADCs, encoders, and similar, to applications on a PC. The framework is based on the Node-on-Chip architecture (link to paper coming). It works by utilizing a dual-port BlockRam in the FPGA, with one port exposed to access the PC (through uTosNet) and the other port exposed to access user-defined modules. This allows easy and generic storage of process variables. Currently two versions of uTosNet are supported: PC side USB converter chip UART FPGA PC side Ethernet Digi Connect ME 9210 microcontroller module SPI FPGA-The uTosNet framework aims at providing a very fast method for interfacing physical components, such as motor drivers, ADCs, encoders, and similar, to applications on a PC. The framework is based on the Node-on-Chip architecture (link to paper coming). It works by utilizing a dual-port BlockRam in the FPGA, with one port exposed to access the PC (through uTosNet) and the other port exposed to access user-defined modules. This allows easy and generic storage of process variables. Currently two versions of uTosNet are supported: PC side USB converter chip UART FPGA PC side Ethernet Digi Connect ME 9210 microcontroller module SPI FPGA
Platform: | Size: 7190528 | Author: Joe | Hits:

[VHDL-FPGA-Verilog] USB_SoftLock

Description: USB SoftLock, 包含VHDL for Xilinx FPGA，上位机驱动以及应用程序-USB SoftLock, Include VHDL for Xilinx FPGA, PC Driver and App
Platform: | Size: 160768 | Author: Eddie | Hits:

[VHDL-FPGA-Verilog] IIC读写EEPROM发送到PC串口

Description: 能实现用IIC读EEPROM并且将读取的数据通过串口发送到PC端，以及在PC端通过串口发送数据给FPGA，再利用IIC将数据写入EEPROM(The program can realize that FPGA read the data from EEPROM by IIC and then send it to PC by UART,and that PC send the data to FPGA by UART and then write the data to EEPROM by IIC)
Platform: | Size: 246784 | Author: lml_234 | Hits:

[VHDL-FPGA-Verilog] irrigation system

Description: 基于FPGA和ARM，通过DHT11测量土壤温湿度等传感器，最终达到智能灌溉，并且能在PC机上进行监测，可通过PC来控制灌溉(Based on FPGA and ARM, soil temperature and humidity sensors were measured by DHT11, and finally intelligent irrigation was realized, and it could be monitored on the PC machine, and irrigation can be controlled by PC)
Platform: | Size: 14558208 | Author: 幽山之隅 | Hits:

[VHDL-FPGA-Verilog] ethernet_loopback

Description: 通过FPGA驱动千兆以太网口，完成SPARTAN6上的UDP数据包闭环测试，即通过网口发送数据包到FPGA，FPGA内部将接收到的数据返回到PC机，建议测试之前添加ARP静态绑定，FGPA内部的IP以及MAC地址在ROM里的COE文档里可以看到，发送端添加了CRC以及整体CHECKSUM的计算(Driven by FPGA Gigabit Ethernet port, UDP SPARTAN6 data packet on the closed loop test, through the network to send data packets to FPGA, FPGA will receive the data back to the PC, the proposed test before adding ARP static binding, FGPA internal IP and MAC address in the COE document in the ROM where you can see, the sender adds CRC and CHECKSUM integral calculation)
Platform: | Size: 23942144 | Author: marktuwen | Hits:

[VHDL-FPGA-Verilog] ad706_test

Description: AD7606的FPGA驱动，AD7606与FPGA通过并行模式连接。FPGA可以将AD采集到的信号转换成电压信号通过串口输出，可通过PC机串口调试助手查看。实测可用(The drive program of AD7606 write by verilog. FPGA can convert the AD7606'sigal to volatage and send the converted signal to PC through uart.)
Platform: | Size: 14983168 | Author: Pgaf | Hits:

[VHDL-FPGA-Verilog] PCI_SEND

Description: 通过PCI数据传输总线，实现PC到PCI板卡的高速数据传输，PCI总线使用9054芯片进行总线协议的转换(Realizing data transmission of PCI)
Platform: | Size: 553984 | Author: 踏破残空 | Hits:

[VHDL-FPGA-Verilog] CH14_RGMII_UDP_TEST

Description: 用xilinx的SPARTAN6 实现的UDP，可通过PC机网络抓包工具进行发送和接收，增加了网络视频传输的接口，具有很好的参考价值(With the Xilinx implementation of the SPARTAN6 UDP, can be sent and received through PC network capture tools, increase the network video transmission interface, has a good reference value)
Platform: | Size: 7115776 | Author: suifeg | Hits:
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